Frequency multipliers are important building blocks in a variety of technologies, for example communication systems. A wide range of frequencies is often desired, thus creating a desire for tuneable frequency multipliers. In general, the noise characteristics of frequency multipliers get worse the wider the tuning range of the generator. Thus, trade-offs have to be made with contemporary frequency multipliers regarding tuning range and noise characteristics. In order to live up to noise specifications, it may thus be necessary to use a plurality of different frequency multipliers to cover a wide frequency band.
The present invention is directed mainly to the field of digital frequency multipliers, and thus, to solve the problems of that category of frequency multipliers. Among those problems, the following could be mentioned:
Usually, only multiplication factors in the form of 2n, where n is an integer, can be obtained. In solutions where factors other than 2n can be obtained, a fixed width pulse is clocked in different integer values of the minimum pulse width. This results in an output frequency spectrum rich in unwanted frequency components. It also adds asymmetry and circuit complexity not suitable for higher frequencies, such as the microwave range.
Also, many suggested digital multipliers are asymmetrical with respect to the different signals, which is particularly troublesome at very high frequencies.
Many solutions are also quite complex, and add jitter. In addition, many digital multipliers use logic circuits such as XOR or OR gates to generate pulses both on rise and fall. This may result in varying curve forms in consecutive pulses in the output of the multiplier.
It should be pointed out that the phrase “frequency multiplier” in this text refers to the pulse frequency in a pulse train.